F00D Processor

This processor is hypothesized to perform most of the cryptography tasks including storing and handing of keys. There is little information about it though. The F00D Processor (named after the  field of the ELF headers) is likely a custom Toshiba MeP core.

You can find an open source f00d protocol implementation at https://github.com/xyzz/f00d

Communication
Communication seems to go through some sort of FIFO register.

Write
To write, put the double word into. Next read  until it returns 0, which indicates the data was read by the F00D processor.

Read
To read, get a double word from. If it returns 0, no data is available. Otherwise, acknowledge that the data has been read by putting the same data into.

Extra ports
In addition to the 0xE0000000 and 0xE0000010, the communication with F00D seems to happen with other ports too.

Protocol
A 32-bit command buffer is defined below. The command is sent to the F00D processor with the method listed above.

Command ID
There are a total of 14 commands. Below are notes on different commands. Commands pass data through the 0x100 shared buffer (set up in command 0).

0x0
This command is used to setup a shared buffer with F00D. First F00D will write in  either 0x200 or 0x600 (and if an error happened, 0x400 ?). If the value 0x600 is written, it will first setup a buffer that contains the f00d secure kernel enp. First it will write 0x1 to  and after that 0x0 to , next, it will wait   return 0 and   return a value <= 0x0. If everything goes alright, it will clear the low 2 bits of the f00d secure kernel enp address (normally at 0x1F850000) and OR it with 0x1 and then write it to. After it, the process is the same that the 0x200. If the value 0x200 is written, it will set the 0x100 sized shared buffer. First the physical address of the buffer is written to  and then command 0x0 is written.

0x1
This command is called by a function inside the SceSblSmSchedForTZS_0xE72F2886 or SceSblSmsched_start (if an error happened while SceSblSmsched is initializing). This command seem to be used to ask the f00d to remove all resource allocated (like shared memory address, secure module loaded, etc), and probably power off or reset it.

0x2
Load sm.

0x3
Load previously suspended sm

0x4
Suspend current sm

0x5
Kill current sm

0x6
Force stop? Called from.

0x7
Unused.

0x8
Unused.

0x9
Set a 0x80 sized shared buffer.

0xA
Set the SCE encrypted revocation list.

Interrupts
There are 4 interrupts that f00d sends. There are only two interrupt handles, however.


 * : handles interrupt 200. This is notifications about current sm status changes (loaded, unloaded, suspended, etc)
 * : handles interrupts 201, 202, 203. This interrupt is sent once an sm command has finished processing (see below).

Executing sm commands
When sm is loaded, you can execute a command it provides by writing into registers 0xE0000014, 0xE0000018, 0xE000001C paddr to the command buffer OR'd with 1.

Command buffer structure:

Once result is available, ARM will get an interrupt 201-203. Read status code from 0xE0000004 (or 0xE0000008, 0xE000000C) and confirm you received it by writing it back to the same register.

Possible results:


 * 1: command executed successfully
 * 3: invalid command ID
 * 5: invalid command buffer paddr (e.g. trying to pass secure memory)
 * 9: SCE_SBL_ERROR_COMMON_EIO

Memory
is allowed access to,  ,  , and. The address checks is likely done in software. F00D has it's own private 128KB memory from  to. F00D SELFs are typically loaded to.

Task states
ARM secure world implements a scheduler for SM tasks. Normally, only one task can run on f00d at a time. The external scheduler running on ARM allows to have multiple tasks at once. The following provides an explanation of various states the task can be in.